[1]
Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, and Chun-Yao Wang, 2021, 4, "Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model," ACM Journal on Emerging Technologies in Computing Systems, vol. 17, no. 2, pp. 1–23.
[2]
Yi-Wen Hung, Yung-Chih Chen, Chi Lo, and Shih-Chieh Chang, 2021, 1, "Dynamic Workload Allocation for Edge Computing," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 29, no. 3, pp. 519–529.
[3]
Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, and Chun-Yao Wang, 2020, 12, "A New Necessary Condition for Threshold Function Identification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 12, pp. 5304–5308.
[4]
Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, and Chun-Yao Wang, 2020, 10, "LOOPLock: LOgic OPtimization based Cyclic Logic Locking," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 10, pp. 2178–2191.
[5]
Yung-Chih Chen, 2020, 5, "SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E103.A(5).
[6]
Yung-Chih Chen, Li-Cheng Zheng, and Fu-Lian Wong, 2019, 11, "Optimization of Threshold Logic Networks with Node Merging and Wire Replacement," ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 6, article 67.
[7]
Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, and Shigeru Yamashita, 2019, 12, "Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 12, pp. 2284-2297.
[8]
Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, and Shih-Chieh Chang, 2018, 6, "Contactless Testing for Prebond Interposers," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 26, no. 6, pp. 1005-1014.
[9]
Yung-Chih Chen, 2018, 7, "Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption," ACM Transactions on Design Automation of Electronic Systems, vol. 23, no. 4, article 52.
[10]
Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, and Chun-Yao Wang, 2018, 12, "On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 26, no. 12, pp. 2842-2852.
[11]
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, and Vijaykrishnan Narayanan, 2017, April, "Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays," IEEE Transactions on VLSI Systems (TVLSI), vol. 25, no. 4, pp. 1477-1489.
[12]
Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, and Yung-Chih Chen, 2016, January, "An Efficient Interpolation-based Projected Sum of Product Decomposition via Genetic Algorithm," Journal of Multiple-Valued Logic and Soft Computing, vol. 27, no. 1, pp. 1-19.
[13]
Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan, 2016, June, "Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays," IEEE Transactions on VLSI Systems (TVLSI), vol. 24, no. 6, pp. 2321-2334.
[14]
Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suma Datta, and Vijaykrishnan Narayanan, 2016, September, "Area-aware Decomposition for Single-Electron Transistor Arrays," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 4, article 70.
[15]
Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, and Chiou-Ting Hsu, 2016, October, "Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks," IEEE Transactions on Multi-Scale Computing Systems, vol. 2 no. 4, pp. 225-233.
[16]
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan, 2015, December, "Synthesis for Width Minimization in the Single-Electron Transistor Array ," IEEE Transactions on VLSI Systems (TVLSI), vol. 32, no. 12, pp. 2862-2875.
[17]
Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen, 2015, April, "Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 4, pp. 615-628.
[18]
Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu, 2014, "Hybrid LUT and SOP reconfigurable architecture," Academia Sinica Journal of Information Science and Engineering (JISE), Vol. 30. I. 1, pp. 65-84.
[19]
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan, 2013, "A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no. 1, article 5.
[20]
Yung-Chih Chen, Chun-Yao Wang, and Ching-Yi Huang, 2013, "Verification of Reconfigurable Binary Decision Diagram-based Single-Electron Transistor Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 10, pp. 1473-1483.
[21]
Yung-Chih Chen, Chun-Yao Wang, 2012, February, "Logic Restructuring Using Node Addition and Removal," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 2, pp.260-270.
[22]
Yung-Chih Chen, Chun-Yao Wang, 2010, November, "Fast Node Merging with Don’t Cares Using Logic Implications,," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 11, pp. 1827-1832.
[23]
Yung-Chih Chen, Chun-Yao Wang, 2008, November, "An Implicit Approach to Minimizing Range-Equivalent Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 1942-1955.
