方劭云Shao-Yun Fang教授Professor
實驗室Laboratory
電子設計自動化實驗室 Electronic Design Automation Lab.
Location : T2-403
Phone : 02-2733-3141 ext. 7939
學術背景與專業概覽Academic & Professional Overview
- 國立臺灣大學電子工程學研究所博士
- PhD, Graduate Institute of Electronic Engineering, National Taiwan University
- 超大型積體電路設計導論、演算法設計與分析、電子設計自動化軟體開發與實作
- Introduction to VLSI Designs, Algorithm Design and Analysis, Software Development for Electronic Design Automation
- 電子設計自動化
- Electronic Design Automation
代表著作Publications
K.-J. Chen and S.-Y. Fang, “Printability Enhancement with Color Balancing for Multiple Patterning Lithography,” accepted, IEEE Trans. on Emerging Topics in Computing (TETC).
T.-C. Yu, S.-Y. Fang, C.-C. Chen, Y. Sun, and P. Chen, “Device Array Layout Synthesis with Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD) , vol. 37, no. 4, pp. 717-728, April 2018.
Z.-W. Lin, S.-Y. Fang, Y.-W. Chang, W.-C. Rao, and C.-H. Kuan, “Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication,” IEEE Trans. Very Large Scale Integration Systems (TVLSI), vol. 26, no. 2, pp. 378-391, February 2018.
K.-L. Lin, S.-Y. Fang, and Y.-X. Hong, “Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly,” IEEE Trans. Circuits and Systems I (TCAS-I), vol. 64, no. 12, pp. 3172-3182, December 2017.
S.-Y. Fang and Kuo-Hao Wu, “Cut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing,” IEEE Trans. Very Large Scale Integrated Systems (TVLSI), vol. 25, no. 2, pp. 581-593, February, 2017.
S.-Y. Fang, Y.-X. Hong, and Y.-Z. Lu, “Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 1., pp. 156-169, January 2017.
I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, “Overlay-aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 9, pp. 1519-1531, September 2016.
I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, “Stitch-Aware Routing for Multiple E-Beam Lithography,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp. 471-482, March 2015.
S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, "A Novel Layout Decomposition Algorithm for Triple Patterning Lithography," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.33, no.3, pp. 397-408, March 2014.
S.-Y. Fang, W.-Y. Chen, and Y.-W. Chang, “Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 2, pp.189-201, February 2013.
S.-Y. Fang, S.-Y. Chen, and Y.-W. Chang, “Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 5, pp. 703-716, May 2012.
T.-C. Yu, S.-Y. Fang, H.-S. Chiu, K.-S. Hu, P. H.-Y. Tai, C.-F. C Shen, and H. Sheng, “Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition,” accepted, ACM/IEEE Design Automation Conference (DAC-2019), Las Vegas, NV, June 2019.
Y.-H. Huang, Z. Xie, G.-Q. Fang, T.-C. Yu, H. Ren, S.-Y. Fang, Y. Chen, and J. Hu, “Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model,” accepted, IEEE/ACM Design Automation and Test in Europe (DATE-2019), Florence, Italy, March 2019.
B.-Y. Yu, Y. Zhong, S.-Y. Fang, and H.-F. Kuo, “Deep Learning-Based Framework for Comprehensive Mask Optimization,” in proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-19), Tokyo, Japan, January 2019.
Z. Xie, Y.-H. Huang, G.-Q. Fang, H. Ren, S.-Y. Fang, Y. Chen, J. Hu, “RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network,” in proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2018), San Diego, CA, November 2018.
S.-Y. Fang and K.-H. Wu, “Guiding Template-induced Design Challenges in DSA-MP Lithography,” in proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2018), Hong Kong, July, 2018.
Y.-K. Chuang, K.-J. Chen, K.-L. Lin, S.-Y. Fang, B. Li, and U. Schlichtmann, “PlanarONoC: Concurrent Placement and Routing Considering Crossing Minimization for Optical Networks-on-Chip,” in proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018.
G.-Q. Fang, Y. Zhong, Y.-H. Cheng, and S.-Y. Fang, “Obstacle-Avoiding Open-Net Connector with Precise Shortest Distance Estimation,” in proceedings of ACM/IEEE Design Automation Conference (DAC-2018), San Francisco, CA, June 2018.
H.-Y. Wu and S.-Y. Fang, “Triple Patterning Lithography-aware Detailed Routing Ensuring Via Layer Decomposability,” in proceedings of IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT-2018), Hsinchu, Taiwan, April 2018.
T.-C. Yu and S.-Y. Fang, “Flip-Chip Routing with IO Planning Considering Practical Pad Assignment Constraints,” in proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-18), Jeju, Korea, January 2018.
K.-H. Wu and S.-Y. Fang, “Simultaneous Template Assignment and Layout Decomposition Using Multiple BCP Materials in DSA-MP Lithography,” in proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2017), Irvine, CA, November 2017.
K.-J. Chen, Y.-K. Chuang, P.-Y. Yu, and S.-Y. Fang, “Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification,” in proceedings of ACM/IEEE Design Automation Conference (DAC-2017), Austin, TX, June 2017.
K.-L. Lin and S.-Y. Fang, “Guiding Template-aware Routing Considering Redundant Via Insertion for Directed Self-Assembly”, in proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2017), January 2017.
S.-Y. Fang and Y.-X. Hong, “Design Optimization Considering Guiding Template Feasibility and Redundant via Insertion for Directed Self-Assembly,” in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS-2016), October 2016.
K.-J. Chen and S.-Y. Fang, “Printability Enhancement with Color Balancing for Multiple Patterning Lithography,” accepted by IEEE Conference on Computer Design (ICCD-2016), Phoenix, AZ, October 2016. (Best Paper Award)
T.-C. Yu, S.-Y. Fang, C.-C. Chen, Y. S, and Poki Chen, “Analog Placement with Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC,” in the 27th VLSI Design/CAD Symposium, Kaohsiung, August 2016.
K.-L. Lin and S.-Y. Fang, “Directed Self-Assembly-aware Routing Considering Redundant Via Insertion,” in the 27th VLSI Design/CAD Symposium, Kaohsiung, August 2016.
K.-J. Chen and S.-Y. Fang, “Post-Decomposition Color Balancing for Multiple Patterning Lithography,” in the 27th VLSI Design/CAD Symposium, Kaohsiung, August 2016.
C.-M. Huang and S.-Y. Fang, “Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography,” in proceedings of IEEE VLSI Design, Automation, and Test (VLSI-DAT-2016), April 2016 (Best Paper Award).
Y.-L. Chang and S.-Y. Fang, “Trim Mask Optimization for Hybrid Multiple Pattering Lithography,” in proceedings of IEEE VLSI Design, Automation, and Test (VLSI-DAT-2016), April 2016.
P.-C. Lin, Y.-H. Pai, Y.-H. Chiu, S.-Y. Fang and C. C.-P. Chen, “Lossless Compression Algorithm Based on Dictionary Coding for Multiple E-Beam Direct Write System,” in proceedings of IEEE/ACM Design Automation and Test in Europe (DATE-2016), March 2016.
S.-Y. Fang, Y.-X. Hong, and Y.-Z. Lu, “Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly,” in proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2015), Austin, November 2015.
Z.-W. Lin, S.-Y. Fang, Y.-W. Chang, W.-C. Rao, and C.-H. Kuan, “Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication,” in proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2015), Austin, November 2015.
Y.-Z. Lu and S.-Y. Fang, “An Optimal Redundant Via Insertion Algorithm for Directed Self-Assembly Lithography,” in the 26th VLSI Design/CAD Symposium, Hualien, August 2015.
Y.-L. Chang and S.-Y. Fang, “Trim Mask Optimization for Hybrid Multiple Pattering Lithography,” in the 26th VLSI Design/CAD Symposium, Hualien, August 2015.
C.-M. Huang and S.-Y. Fang, “Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography,” in the 26th VLSI Design/CAD Symposium, Hualien, August 2015.
Y.-W. Chang, R.-G. Liu, and S.-Y. Fang, “EUV and E-Beam Manufacturability: Challenges and Solutions,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), San Francisco, CA, June 2015.
S.-Y. Fang, “Cut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing,” in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2015), Chiba, Japan, 2015.
S.-Y. Fang, Y.-S. Tai, and Y.-W. Chang, “Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning,” in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2015), Chiba, Japan, 2015.
S.-Y. Fang, Y.-S. Tai, and Y.-W. Chang, “Spacer-is-Metal (SIM)-Type Layout Decomposition for Self-Aligned Double Patterning,” in the 25th VLSI Design/CAD Symposium, Taichung, August 2014.
I.-J. Liu, S.-Y. Fang, and Y.-W. Chang, “Overlay-aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, June 2014.
S.-Y. Fang, I.-J. Liu, and Y.-W. Chang, “Stitch-Aware Routing for Multiple E-Beam Lithography,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.
S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, “Simultaneous OPC- and CMP-aware Routing Based on Accurate Closed-Form Modeling,” in Proceedings of ACM International Symposium on Physical Design (ISPD-2013), pp.77-84, The Ridge Tahoe, NV, March 2013. (Best Paper Nominee)
S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, “Accurate Closed-Form Modeling for Simultaneous OPC- and CMP-Aware Routing,” in the 23th VLSI Design/CAD Symposium, Pingtong, August 2012.
S.-Y. Fang and Y.-W. Chang, “Simultaneous Flare Level and Flare Variation Minimization with Dummification in EUVL,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), pp. 1175-1180, San Francisco, CA, June 2012.
S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen, “A Novel Layout Decomposition Algorithm for Triple Patterning Lithography,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), pp. 1181-1186, San Francisco, CA, June 2012.
S.-Y. Fang, T.-F. Chien, and Y.-W. Chang, “ECO Timing and Mask Cost Optimization with Redundant Wires,” in the 21th VLSI Design/CAD Symposium, Kaohsiung, August 2010. (Best Paper Award)
S.-Y. Fang, W.-Y. Chen, and Y.-W. Chang, “Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication,” in Proceedings of ACM International Symposium on Physical Design (ISPD-2012), pp.9-16, Napa, CA, March 2012. (Best Paper Nominee)
S.-Y. Fang, W.-Y. Chen, and Y.-W. Chang, “Subfield Scheduling with Blocked Region Consideration for Electron-Beam Photomask Fabrication,” in the 22th VLSI Design/CAD Symposium, Chiayi, August 2011.
S.-Y. Fang, T.-F. Chien, and Y.-W. Chang, “Redundant-Wires-Aware ECO Timing and Mask Cost Optimization,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), pp. 381-386, San Jose, November 2010.
尚無資料No records