組別/跨組別 Area
積體電路與系統組/
辦公室 Office
T2-501-1
電話 Phone
02-2730-3648
Office Hour
Tue. 13:30-15:30
實驗室 Laboratory
可依賴性暨安全性計算實驗室 Dependable and Secure Computing Lab.
Location : T2-310
Phone : 02-2733-3141 ext. 6825
學術背景與專業概覽
Academic and Professional Overview
| 學、經歷 | |
| 課程 | |
| 研究領域 |
| Education & Experience | |
| Course | |
| Research Areas |
著作 Publications
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Journals/
Proceedings/
Scholarly Works
研究計畫 Projects
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NSC/
Industry
[1]
Y. Ikiri, F. Sako, M. Hashizume, H. Yotsuyanagi, S. K. Lu, T. Yazaki, Y. Ikeda, and Y. Uematsu, "Open Defect Detection in Assembled Circuit Boards with Built-In Relaxation Oscillators," IEEE Trans. Components, Packaging and Manufacturing Technology," vol. 11, no. 6, pp. 931-943, June 2021.
[2]
S. K. Lu, H. P. Li, K. Miyase, C. L. Hsu, and C. T. Sun, "Fault-Aware Dependability Enhancement Techniques for Phase Change Memory," J. Electronic Testing: Theory and Applications (JETTA), vol. 37, no. 4, Aug. 2021. (to appear, SCI, Full Paper)
[3]
M. Kanda, M. Hashizume, F. A. B. ALI, H., and S. K. Lu, "Open Defect Detection Not Utilizing Boundary Scan Flip-flops in Assembled Circuit Boards," IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 10, no. 5, pp. 895-907, May 2020.
[4]
S. K. Lu, S. C. Yu, C. L. Hsu, C. T. Sun, M. Hashizume, and H. YOTSUYANAGI, "Fault-Aware Dependability Enhancement Techniques for Flash Memories," IEEE Trans. VLSI Systems, vol. 28, no. 3, pp. 634-645, Mar. 2020. (SCI, Full paper)
[5]
S. K. Lu, H. K. Huang, C. L. Hsu, C. T. Sun, and K. Miyase, "Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM," J. Electronic Testing: Theory and Applications (JETTA), vol. 35, no. 4, pp 485–495, Aug. 2019. (SCI, Full Paper)
[6]
S. K. Lu, S. X. Zhong, and M. Hashizume, "Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories," J. Electronic Testing: Theory and Applications (JETTA), vol. 34, no. 5, pp. 559-570, Oct. 2018. (SCI, Full Paper)
[7]
S. K. Lu, H. C. Jheng, H. W. Lin, and M. Hashizume,"Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories," J. Electronic Testing: Theory and Applications (JETTA), vol. 34, no. 4, pp. 435-446, July 2018. (SCI, Full Paper)
[8]
Fara Ashikin Binti Aliy, M. Hashizume, Hiroyuki YOTSUYANAGI, S. K. Lu, and Z. Roth, "Design for Testability of Open Defects at Interconnects in 3D Stacked ICs," IEICE Trans. Information and Systems, vol. E101-D, no. 8, pp. 2053-2063, Aug. 2018. (SCI, Full Paper)
[9]
M. Hashizume, S. Suenaga, H. Yotsuyanagi, A. Ono, S. K. Lu, Z. Roth, "A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs," IEICE Trans. Information and Systems, vol. E99-D, no. 11, pp. 2723-2733, Nov. 2016. (SCI, Full Paper)
[10]
S. K. Lu, C. J. Tsai, and M. Hashizume, "Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories," IEEE Trans. VLSI Systems, vol. 24, no. 8, pp. 2726-2734, Aug. 2016. (SCI, Full paper)
[11]
S. K. Lu, T. L. Li, M. Hashizume, and J. L. Chen, "Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs," IEEE Trans. Computers, vol. 64, no. 5, pp. 1230-1240, May 2015. (SCI, Full paper)
[12]
Y. W. Ma, J. L. Chen, C. H. Chou, and S. K. Lu, "Study on Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing," IEEE Systems Journal, vol. 8, no. 1, pp. 219-224, Mar. 2014. (SCI, Full Paper))
[13]
S. K. Lu, M. Hashizume, T. L. Li, and J. L. Chen, "An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs," IEICE Trans. Information and Systems, vol.E96-D, no.9, pp. 2026-2030, Sep. 2013.
[14]
S. K. Lu and H. H. Huang, "Synergistic Reliability and Yield Enhancement Techniques for Embedded Memories," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 165-169, Jan. 2013
[15]
S. K. Lu, T. W. Chang, and H. Y. Hsu, "Yield Enhancement Techniques for 3-Dimensional Random Access Memories," Microelectronics Journal, vol. 52, pp. 1065-1070, May 2012. (SCI, Full paper)
[16]
S. K. Lu, Z. Y. Wang, and Y. M. Tsai, "Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 4, pp. 620-629, Apr. 2012. (SCI, Full paper)
[17]
S. K. Lu and Y. C. Huang, " Improving Reusability of Test Symbols for Test Data Compression," Journal of Information Science and Engineering, Vol. 28 No. 2, pp. 351-364, Mar. 2012.(SCI, Full paper)
[18]
S. K. Lu, Y. M. Chen, S. Y. Huang, and C. W. Wu, "Speeding-up Emulation-Based Diagnosis Techniques for Logic Cores," IEEE Design and Test of Computers, pp. 88-97, July-August, 2011.
[19]
S. K. Lu, etc., Efficient BISR Techniques for Embedded Memories Considering Cluster Faults,” IEEE Trans. VLSI Systems, vol. 18, no. 2, pp. 184-193, Feb. 2010. (SCI, Full paper)
[20]
S. K. Lu and W. Y. Liu, "Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain," Journal of Electronic Science and Technology,vol. 7, no. 4, pp. 291-296, Dec. 2009 (EI, Full paper)
[21]
S. K. Lu, Y. C. Hsiao, C. H. Liu, and C. L. Yang, “Low-Power Built-In Self-Test Techniques for Embedded SRAMs,” VLSI Design, vol. 2007, pp. 1-6, 2007. (SCI, Full paper)
[22]
S. K. Lu and C. H. Hsu, “Fault Tolerance Techniques for High Capacity RAMs,” IEEE Trans. Reliabilities, vol. 55, no. 2, pp. 293-306, June 2006. (SCI, Full paper)
[23]
S. K. Lu, etc, “Efficient Built-In Redundancy Analysis for Embedded Memories with 2-D Redundancy,” IEEE Trans. VLSI Systems. vol. 14, no. 1, pp. 34-42, Jan. 2006. (SCI, Full paper)
[24]
S. K. Lu, H. C. Wu, and Y. C. Tsai, “Multiple Fault Detection and Diagnosis Techniques for Lookup Table FPGA’s,” IEE Proceedings- Computers & Digital Techniques, vol. 152, no. 5, pp. 577-584, Sep. 2005. (SCI, Full paper)
[25]
S. K. Lu, J. S. Shih, and S. C. Huang, “Design-for-Testability and Fault-Tolerant techniques for FFT Processors,” IEEE Trans. VLSI Systems, vol. 13, no. 6, pp. 732-741, June 2005. (SCI, Full paper)
[26]
S. K. Lu and S. J. Yan, “Design and Implementation of a Scalable High-Performance AES Cipher Chip,” Fu Jen Studies, no. 38, pp. 179-196, Dec. 2004.
[27]
S. K. Lu, “Defect Level Prediction Using Multi-Model Fault Coverage,” IEICE Transactions on Information and Systems, vol. W87-D, no. 6, June 2004. (SCI, Full Paper, Accepted)
[28]
S. K. Lu and Chung-Yin Lee, “Modeling Economics of DFT and DFY: A Profit Perspective,” IEE Proceedings - Computers & Digital Techniques, vol. 151, no. 2, pp. 119-126, Mar. 2004. (SCI, Full paper)
[29]
S. K. Lu, “Delay Fault Testing for CMOS Iterative Logic Arrays with a Constant Number of Patterns,” IEICE Transactions on Information and Systems, vol. E86-D, no. 12, pp. 2659-2665, Dec. 2003. (SCI, Full paper)
[30]
S. K. Lu, “Built-In Self-Repair Techniques for Embedded RAMs,” IEE Proceedings- Computers & Digital Techniques, vol. 150, no. 4, pp. 201-208, July 2003. (SCI, Full paper)
[31]
S. K. Lu, “A Novel Built-In Self-Test Approach for Embedded RAMs,” Journal of Electronic Testing: Theory and Application, vol. 19, pp. 315-324, June 2003. (SCI, Full paper)
[32]
H. C. Kao, M. F. Tsai, S. Y. Huang, C. W. Wu, W. F. Chang, and S. K. Lu, “Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults,” Journal of Information Science and Engineering, vol. 19, pp. 571-587, May 2003. (SCI, Full paper)
[33]
S. K. Lu and C. Y. Chen, “Design and Implementation of a Two-Dimensional DCT/IDCT Processor for Video Compression Systems,” Fu Jen Studies, no. 36, pp. 49-72. Dec. 2002.
[34]
S. K. Lu and J. S. Shi, "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGA’s,” VLSI Design, vol. 15, pp. 397-406, Aug. 2002. (SCI, Full paper)
[35]
F. M. Yeh, S. K. Lu, and S. Y. Kuo, "OBDD-based Evaluation of K-terminal Network Reliability ", IEEE Trans. Reliabilities, vol. 51, no. 4, pp. 443-451, Dec. 2002. (SCI, Full paper)
[36]
S. K. Lu and M. H. Cheng, “Logic Diagnosis Techniques Based on BIST Environments,” Integrated Circuit Design Magazine, vol. 18, pp. 52-61, Sep. 2001.
[37]
S. K. Lu and T. Y. Lee, “A Profit Evaluation System (PES) for VLSI Systems at Early Design Stage,” Fu Jen Studies, no. 34, pp. 69-81. Dec. 2000.
[38]
S.-K. Lu and J. S. Shi, "Testing Configurable LUT-Based FPGAs", Journal of Information Science and Engineering, vol. 16, no. 5, pp. 142-153, Sep. 2000. (SCI, Full paper)
[39]
J. F. Li, S. K. Lu, S. A. Huang, and C. W. Wu, “Easily Testable and Fault Tolerant FFT Butterfly Networks,” IEEE Trans. Circuits and Systems II, vol. 47, no. 9, pp. 919-929, Sep. 2000. (SCI, Full paper)
[40]
S. Y. Kuo, S. K. Lu, and F. M. Yeh, "Determining Terminal-Pair Reliability Based on Edge Expansion Diagrams using OBDD", IEEE Trans. Reliabilities, vol. 48, No. 3, Sep. 1999, pp. 234-246. (SCI, Full paper)
[41]
S.-K. Lu, S.-Y. Kuo and C.-W. Wu, “Fault-tolerant interleaved memory systems with two level redundancy,“ IEEE Trans. Computers, pp. 1028-1034, Sep. 1997.
[42]
S.-K. Lu, C.-W. Wu and R.-Z. Hwang, “Cell-delay fault testing for iterative logic arrays“, J. Electronic Testing: Theory and Applications (JETTA), pp. 311-316, 1996.
[43]
S.-K. Lu, J.-C. Wang and C.-W. Wu, “C-testable design techniques for iterative logic arrays“, IEEE Trans. VLSI Systems, vol. 3, no. 2, pp.146-152, vol. 3, no. 1, Mar. 1995.
[44]
S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Enhancing testability of VLSI arrays for fast Fourier transform“, IEE Proc. Part E, vol. 140, no. 3, pp. 161-166, May. 1993.
[1]
F. Sako, Y. Ikiri, M. Hashizume, H. Yotsuyanagi, H. Yokoyama and S. -K. Lu, "Temperature Sensing with a Relaxation Oscillator in CMOS ICs," 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Nagoya, Japan, 2020, pp. 141-144.
[2]
S. K. Lu, Z. L. Tsai, C. L. Hsu and C. T. Sun, "Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory," 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-2, Aug. 2020.
[3]
S. K. Lu, Z. L. Tsai, C. L. Hsu, and C. T. Sun, "ECC Caching Techniques for Protecting NAND Flash Memories," in Proc. IEEE Int'l Test Conf. in Asia (ITC-Asia), pp. 47-52, Sep. 2020.
[4]
M. Kanda, D. Yabui, M. Hashizume, H. Yotsuyanagi and S. K. Lu, "Stand-by Mode Test Method of Interconnects between Dies in 3D ICs with IEEE 1149.1 Test Circuits," 2018 IEEE CPMT Symposium Japan (ICSJ), Kyoto, 2018, pp. 189-192.
[5]
Y. Matsumoto, M. Hashizume, H. Yotsuyanagi and S. K. Lu, "Resistive Open Defect Detection in SoCs by a Test Method Based on Injected Charge Volume after Test Input Application," 2018 IEEE CPMT Symposium Japan (ICSJ), Kyoto, 2018, pp. 141-142.
[6]
M. Kanda, M. Hashizume, H. Yotsuyanagi and S. K. Lu, "A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs," IEEE CPMT Symposium Japan (ICSJ), pp. 137-138, 2017.
[7]
K. Ohtani, N. Osato, M. Hashizume, H. Yotsuyanagi and S. K. Lu, "A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume," International Symposium on Communications and Information Technologies (ISCIT), pp. 1-5, 2017.
[8]
S. K. Lu, Z. L. Tsai, and K. Miyase, "Skewed ECC Techniques for Reliability Enhancement of Flash Memory," in Proc. IEEE Int'l Workshop on Automotive Reliability & Test (ART), Nov. 2019.
[9]
H. Soneda, M. Hashizume, H. Yotsuyanagi, and S. K. Lu, “Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes,” in Proc. IEEE 3D Systems Integration Conf., Oct. 2019. (Student Poster Award)
[10]
S. K. Lu, W. C. Tsai, C. L. Hsu, C. T. Sun, and K. Miyase, "Scrubbing-Based Reliability and Yield Enhancement Techniques for Flash Memory," in Proc. Int'l Conf. on Advanced Technology Innovation, July 2019.
[11]
K. Miyase, Y. Kawano, S. K. Lu, X. Q. Wen, and S. Kajihara, “A Static Method for Analyzing Hotspot Distribution on the LSI,” in Proc. IEEE Int’l Conf. on Test in Asia, pp. 73-78, Sep. 2019.
[12]
S. K. Lu, H. P. Li, and K. Miyase, "Progressive ECC Techniques for Phase Change Memory," in Proc. Asian Test Symposium (ATS), pp. 161-166, Oct. 2018.
[13]
S. K. Lu, W. C. Tsai, K. Miyase, and N. J. Wang, “Virtual Fault Scrubbing Techniques for Enhancing Reliability and Yield of Flash Memory,” in Proc. IEEE Workshop on RTL and High-Level Testing (WRTLT), pp. 1-4, Oct. 2018.
[14]
S. K. Lu, H. P. Li, and K. Miyase, "Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory," in Proc. IEEE Int'l Symp. on On-Line Testing and Robust System Design," pp. 1-2, July 2018.
[15]
S. K. Lu, H. K. Huang, and C. J. Lai," Address Address -Based Refresh Refresh Refresh Refresh Refresh Techniques for Mitigation of Data Retention Faults and Low Data Retention Power, in Proc. VLSI/CAD Symposium, Aug. 2017.
[16]
M. Kanda, M. Hashizume, H. Yotsuyanagi and S. K. Lu, "A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type," in Proc. IEEE Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Sep. 2017, pp. 1-4.
[17]
A. Kambara, H. Yotsuyanagi, D. Miyoshi, M. Hashizume, and S. K. Lu, "Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs," in Proc. Asian Test Symposium (ATS), Nov. 2017, pp. 242-247.
[18]
S. K. Lu, S. C. Yu, M. Hashizume†, and H. YOTSUYANAGI, "Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories," in Proc. Asian Test Symposium (ATS), Nov. 2017, pp. 254-259. (Best Paper Award)
[19]
S. K. Lu and H. K. Huang, "Adaptive Block-Based Refresh Techniques for Mitigation of Data Retention Faults and Reduction of Refresh Power," in Proc. IEEE Int'l Test Conference in Asia (ITC-Asia), Sep. 2017, pp. 101-106.
[20]
C. Zheng, S. Y. Huang, S. K Lu, T. C. Wang, K. Tsai and W. Cheng, "Online slack-time binning for IO-registered die-to-die interconnects," IEEE International Test Conference (ITC), pp. 1-8, Nov. 2016.
[21]
S. K. Lu, S. X. Zhong, and M. Hashizume, "Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories," in Proc. Asian Test Symposium (ATS), pp. 287-292, Nov. 2016.
[22]
Takumi Miyabe, Masaki Hashizume, Hiroyuki Yotsuyanagi,Shyue-Kung Lu, and Z Vi Roth, "A Built-in Electrical Test Circuit for Detecting Open Leads in Assembled PCB Circuits with RC Integrator," in Proc. of ICEP 2016, pp. 451-455, 2016.
[23]
S. K. Lu, H. W. Lin, and M. Hashizume, "An Enhanced Built-In Self-Repair Technique for Yield and Reliability Improvement of Embedded Memories," in Proc. IEEE International Conference on ASIC, Nov. 2015, pp. 1-4.
[24]
S. K. Lu, C. J. Tsai, and M. Hashizume, "Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories," in Proc. IEEE Asian Test Symposium, Nov. 2015, pp. 49-54.
[25]
D. Suga, M. Hashizume, H. Yotsuyanagi, and S. K. Lu, "Electrical Interconnect Test Method of 3D ICs by Injected Charge Volume," in Proc. IEEE 2015 International 3D Systems Integration Conference (3DIC 2015), pp. TS8.19.1-5, Aug. 2015.
[26]
K. Nanbara, A. Odoriba, M. Hashizume, H. Yotsuyanagi, S. K. Lu, "Electrical Interconnect Test of 3D ICs Made of Dies without ESD Protection Circuits with a Built-in Test Circuit," Proc. of IEEE 2015 International 3D Systems Integration Conference (3DIC 2015), pp. TS8.22.1-5, Aug. 2015.
[27]
Yuki Ikiri, Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Tetsuo Tada and Shyue-Kung Lu,"Repair Circuit of TSVs in a 3D Stacked Memory IC", Proc. of International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2015), pp.431-434,Seoul, Korea, June 2015.
[28]
S. K. Lu, S. L. Lin, H. W. Lin, and M. Hashizume, "Hybrid Scrambling Technique for Increasing the Fabrication Yield of NROM-Based ROMs," in Proc. IEEE Int'l Symp. on VLSI Design, Automation and Test (VLSI-DAT). pp. 1-4, Apr. 2015.
[29]
Akihiro Odoriba, Shoichi Umezu, Masaki Hashizume, Hiroyuki Yotsuyanagi, Fara Ashikin Binti Ali, and Shyue-Kung Lu : " A. Odoriba, S. Umezu, M. Hashizume, H. Yotsuyanagi, F. Ashikin, B. Ali, and S. K. Lu, "A Testable Design for Electrical Interconnect Tests of 3D ICs", Proc. of 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference(ICEP-IAAC2015), pp. 718-722, Kyoto, Japan, April 2015.
[30]
15. K. Nambara, S. Umezu, H. Yotsuyanagi, M.Hashizume and Shyue-Kung Lu, "Threshold Value Estimation of Electrical Interconnect Tests with Scan FFs," Proc. of IEEE CPMT Symposium Japan 2014, pp.158-161, Kyoto, Japan, 2014. (Young Scholar Award)
[31]
S. K. Lu, H. C. Jheng, H. W. Lin, Masaki. Hashizume, and Seiji Kajihara, “Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories,” in Proc. Asian Test Symposium (ATS 2014), pp. 137-142, Nov. 2014.
[32]
S. K. Lu, H. M. Li, Masaki Hashizume, J. H. Hong, and Z. R. Tsai, “Efficient Post-bond Test Techniques for Interposer-Based 2.5D ICs,” in Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, Apr. 2014.
[33]
Shiraishi, Y. ; Hashizume, M. ; Yotsuyanagi, H. ; Tada, T.; S. K. Lu, “Electrical test method of open defects at data buses in 3D SRAM IC,” in Proc. IEEE Int’l Conf. on Electronics Packaging (ICEP), pp. 235-238, Apr. 2014.
[34]
Masaki Hashizume, Yudai Shiraishi, Hiroyuki Yotsuyanagi, Hiroshi Yokoyama, Testuo Tada and Shyue-Kung Lu, "Threshold Setting of Electrical Test Method for Open Defects at Data Bus in 3D SRAM IC," in Proc. 2014 IEEE Workshop on RTL and High-Level Testing (WRTLT 2014), Hangghou, Nov. 2014.
[35]
S. K. Lu, U. C. Lu, S. W. Pong, and H. C. Cheng, "Efficient Test and Repair Architectures for 3D TSV-Based Random Access Memories," in Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, Apr. 2013.
[36]
S. K. Lu, H. C. Jheng, and M. Hashizume, “Fault Scrambling Techniques for Yield Enhancement of Embedded Memories,” in Proc. IEEE Asian Test Symposium, pp. 215-220, Nov. 2013.
[37]
E. Haraguchi, M. Hashizume, K. Manabe, H. Yotsuyanagi, T.Tada, S. K. Lu, and Z. Roth, “Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC, in Proc. CPMT Symposium Japan (ICSJ), pp. 1-4, Nov. 2013.
[38]
Suenaga, S. ; Hashizume, M. ; Yotsuyanagi, H. ; S. K. Lu ; Roth, Z., “DFT for supply current testing to detect open defects at interconnects in 3D Ics,” in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), pp. 60-63, Dec. 2013.
[39]
S. K. Lu; M. C. Chen; Y. C. Chen, “Error-tolerance evaluation and design techniques for motion estimation computing arrays,” in Proc. IEEE On-Line Testing Symposium (IOLTS), pp. 167-168, July 2013.
[40]
Hashizume, M. ; Konishi, T. ; Yotsuyanag, H.; S. K. Lu, “Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs, in Proc. IEEE Asian Test Symposium, pp. 13-18, Nov. 2013.
[41]
S. K. Lu, T. L. Li, and Pony Ning, "Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs," in Proc. IEEE Asian Test Symposium, pp. 308-313, Nov. 2012.
[42]
C. W. Wu, S. K. Lu, and J. F. Li, "On Test and Repair of 3D Random Access Memory," in Proc. ASP-DAC, pp. 744-749, Feb. 2012. (invited paper)
[43]
S. K. Lu, H. H. Huang, and T. L. Li, "Synergistic Techniques for Yield and Reliability Enhancement of Embedded SRAMs," 6th VLSI Test Technology Workshop (VTTW2012), July 2012.
[44]
S. K. Lu, T. W. Chang, and H. Y. Hsu, "Efficient Built-In Self-Repair Techniques for Yield Enhancement of 3D Random Access Memories," in Proc. Int'l Conf. on Dependable Systems and Networks (DSN), pp. 103-106, June 2011.
[45]
H. Y. Hsu, S. K. Lu, and S. Y. Kuo, "High-Speed Testing Techniques for Content-Addressable Memories," in Proc. Int'l Conf. on Dependable Systems and Networks (DSN), pp. 87-90, June 2011.
[46]
S. K. Lu and Zhen-Qun Quan, "Concurrent Error Detection Techniques for Array Multipliers," in Proc. 2011 Intelligent Living Technology Conference.
[47]
S. K. Lu, J. Y. Wang, and Y. M. Tsai, "Yield Enhancement Techniques for Multiple Repairable Memory Cores," 4th VLSI Test Technology Workshop (VTTW2010), Aug. 2010.
[48]
M. Y. Dong, S. H. Yang, and S. K. Lu, "Testable and Built-In Self-Test Techniques for Motion Estimation Computing Arrays," in Proc. IEEE Eleventh Workshop on RTL and High-Level Testing, Dec. 2010.
[49]
Z. Y. Wang, Y. M. Tsai, Y. C. Hsiao, and S. K. Lu, “Wireless Built-In Self-Repair Techniques for Embedded RAMs, 8th IEEE Int’l Conf. ASIC, pp. 573-576, Oct. 2009.
[50]
Z. Y. Wang, Y. M. Tsai and S. K. Lu, "Built-In Self-Repair Techniques for Heterogeneous Memory Cores,” in Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2009), pp. 69-74, Nov. 2009.
[51]
S. K. Lu and H. S. Fu, “Low-Complexity Computation Techniques for Block Matching Motion Estimation,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE 2009), pp. 681-682, May 2009.
[52]
S.K. Lu, H. M. Chuang, G. Y. Lai, B. T. Lai, and Y. C. Huang, "Efficient Test Pattern Compression Techniques Based on Complementary Huffman Coding," in Proc. 3rd VLSI Test Technology Workshop (VTTW2008), July 2009.
[53]
S. K. Lu and G. Q. Lin, “Built-In Self-Repair Techniques for Content Addressable Memories,” in Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test (VLSI-DAT) pp. 267-270, Apr. 2009.
[54]
S. K. Lu, W. Y. Liu, J. Y. Huang, and J. J. Hong, “Testable Design and BIST Techniques for Systolic Motion Estimators in the Transform Domain,” in Proc. IEEE Int’l Conf. on Testing and Diagnosis (ICTD2009), pp. 1-4, Apr. 2009.
[55]
S. K. Lu, H. M. Chuang, G. Y. Lai, B. T. Lai, and Y. C. Huang, “Efficient Test Pattern Compression Techniques Based on Complementary Huffman Coding,” in Proc. IEEE Int’l Conf. on Testing and Diagnosis (ICTD2009).
[56]
P. Y, Yeh, B. Y. Yeh, S. Y. Kuo, and S. K. Lu, "Scalable arithmetic cells for iterative logic array," in Proc. IEEE Int'l Conf. on Electrical and Computer Engineering, Dec. 2008, pp. 325-330.
[57]
P. Y, Yeh, B. Y. Yeh, S. Y. Kuo, and S. K. Lu, "Novel C-Testable Design for H.264 Integer Motion EWstimation," in Proc. IEEE Int'l Conf. on Electrical and Computer Engineering, Dec. 2008, pp. 735-740.
[58]
S. K. Lu, G. Q. Lin, and S. Y. Kuo, ”Yield Enhancement Techniques for Content-Addressable Memories,” in Proc. IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN), pp. 27-28, June 2008.
[59]
M. Y. Dong, S. H. Yang, and S. K. Lu, “Design-for-Testability Techniques for Motion Estimation Computing Arrays,” in Proc. Int. Conf. Comm., Circuits, and Systems, pp. 161-164, May 2008.
[60]
S. K. Lu, Y. C. Hsiao, and C. L. Yang, “Efficient BISR Techniques for Embedded Memories Considering Cluster Faults,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2007), pp. 224-231, Dec. 2007.
[61]
C. L. Yang and S. K. Lu, “Modified Essential Spare Pivoting Algorithm for Embedded Memories with Global Block-Based Redundancy,” Proc. 16th VLSI/CAD Symposium, Aug. 2007.
[62]
S. K. Lu, M. Y. Dong and S. H. Yang, “Architectures and Testable Design Techniques for Motion Estimation Computing Arrays,” 1st VLSI Test Technology Workshop, July 2007.
[63]
C. L. Yang and S. K. Lu, “Global Block-Based Built-In Self-Repair Techniques for Embedded SRAMs,” in Proc. IASTED Conf. on "Circuits, Signals and Systems (CSS 2007), pp. 76-79, July 2007.
[64]
S. K. Lu, J. H. Lieo, J. L. Yang, and Y. C. Hsao” Low-Power Built-In Self-Test Techniques for Embedded SRAMs,” in Proc. 7th Workshop on RTL and High-Level Testing, (to appear)
[65]
S. K. Lu, T. Y. Chen, and W. Y. Liu, “Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits,” in Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2006), pp. 97-104, Dec. 2006.
[66]
M. W. Wu, Y. N. Huang , I. Y. Chen3, S. K. Lu, and S. Y. Kuo, “A Scalable Port Forwarding for P2P-based Wi-Fi Applications,” in Proc. IEEE Int’l Conf. on Wireless Algorithms, Systems and Applications (WASA’06), Xi’an, Aug. 2006.
[67]
S. K. Lu, C. L. Yang, and H. W. Lin, “Efficient BISR Techniques for word-Oriented Embedded Memories with Hierarchical Redundancy, in Proc. IEEE Int’l Conf. on Computer and Information Science (ICIS2006), pp. 355-360, July 2006.
[68]
S. K. Lu, W. Y. Liu, and T. Y. Chen, Efficient BIST Techniques for Two-Dimensional DCT/IDCT Processors,” in Proc. 2006 Intelligent Living Technology Conference, pp. 33-37, June 2006.
[69]
P. Y. Yeh, B. Y. Yeh, I. Y. Cheng*, S. Y. Kuo, and S. K. Lu, “Testable Design Techniques for Variable Block Size Motion Estimator Used in H.264/AVC,” 5th International Conference on Instrumentation, Measurement, Circuits, and Systems (IMCAS '06), Apr. 16-18, 2006.
[70]
S. K. Lu and M. Y. Dong, “Efficient Built-In Self-Test Techniques for Sequential Fault Testing of Iterative Logic Arrays,” 5th International Conference on Instrumentation, Measurement, Circuits, and Systems (IMCAS '06), Apr. 16-18, 2006.
[71]
M. W. Wu, Y. Huang, S. K. Lu, I. Y. Chen, and S. Y. Kuo, "A multi-faceted approach towards spam-resistible mail," in Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2005), pp. 1-9, Nov. 2005.
[72]
S. K. Lu, H. C. Wu, and Y. C. Tsai, “Fault Grading and Test Configuration Generation for Embedded FPGAs,” Proc. 16th VLSI/CAD Symposium, Aug. 2005.
[73]
S. K. Lu and S. C. Huang, “Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs,” Proc. 16th VLSI/CAD Symposium, Aug. 2005.
[74]
S. K. Lu, Y. C. Tsai, and S. C. Huang, “A BIRA Algorithm for Embedded Memories with 2-D Redundancy,” Proc. Int’l Workshop on Memory Technology, Design and Testing (MTDT’05), pp. 121-126, Aug. 2005.
[75]
S. K. Lu, and S. C. Huang, “A Built-In Self-Repair Compiler for Embedded Memories,” in Proc. 6th Workshop on RTL and High-Level Testing, pp. 180-183, July 2005.
[76]
S. K. Lu, H. C. Wu, and Y. C. Tsai, “Fault Detection and Diagnosis Techniques for Embedded FPGA’s,” Proc. Asian Test Symposium, pp. 414-419, Nov. 2004.
[77]
S. K. Lu, H. W. Lin, Y. C. Tsai, and K. H. Wang, “Efficient Built-In Redundancy Analysis for Embedded Memories with 2-D Redundancy,” Proc. Int’l SOC Design Conf., pp. 380-384, Oct. 2004.
[78]
S. K. Lu and S. C. Huang, “Built-In Self-Test and Repair (BISTR) Techniques for Embedded RAMs,” Proc. Int’l Workshop on Memory Technology, Design and Testing (MTDT’04), pp. 60-64, Aug. 2004.
[79]
S. K. Lu and M. J. Lu, “Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model,” Proc. IEEE Int’l Conf. Electronic Design, Test and Applications (DELTA2004), pp. 81-84, Jan. 2004.
[80]
S. K. Lu, Chien-Hung Yeh and Han-Wen Lin, “Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2004), pp. 321-326, Mar. 2004.
[81]
S. K. Lu, H. C. Wu, and Y. C. Tsai, “Efficient Fault Simulation Techniques and Test Configuration Generation for Embedded FPGAs,” Proc. 46th IEEE Midwest Symposium on Circuits and Systems,” Dec. 2003.
[82]
S. K. Lu and Y. C. Tsai, “Built-In Self-Repair Techniques for High-Density Embedded RAMs,” VLSI/CAD Symposium, Aug. 2003.
[83]
S. K. Lu, J. L. Chen, C. W. Wu, W. F. Chang, and S. Y. Huang, “Combinational Circuit Fault Diagnosis Using Logic Emulation,” Proc. Int. Symp. Circuits and Systems, pp. V-549-V-552, May 2003.
[84]
S. K. Lu and M. J. Lu, “Testing Iterative Logic Arrays for Delay Faults with a Constant Number of Patterns,” Proc. International Symposium on Electronic Materials and Packaging, pp. 492-498, Dec. 2002.
[85]
S. K. Lu and Jen-Hong Yeh, “Enhancing Delay Fault Testability for Iterative Logic Arrays,” Proc. Pacific Rim International Symposium on Dependable Computing, pp. 283-290, Dec. 2002.
[86]
S. K. Lu and Chung-Yang Chen, “Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs,” Proc. Asian Test Symposium, pp. 236-241, Nov. 2002.
[87]
S. K. Lu and Jen-Hong Yeh, “Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks,” Proc. Asian Test Symposium, pp. 230-235, Nov. 2002.
[88]
C. H. Hsu and S. K. Lu, “Fault-Tolerance Design of Memory Systems Based on DBL Structures,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems, Oct. 2002, pp. 221-224.
[89]
C. H. Hsu, S. K. Lu, and S. Y. Kuo, “Novel Fault-Tolerant Techniques for High Capacity RAMs,” Proc. Pacific Rim Conference on Parallel and Distributed Computing (PRDC2001), pp. 11--18, Seoul, Korea, Dec. 2001.
[90]
I. M. Chen, S. K. Lu, “Logic Diagnosis Based on Hardware Emulator,” Proc. 2001 VLSI/CAD Workshop, Taoyuan, Taiwan, Aug. 2001.
[91]
C. H. Hsu, S. K. Lu, and M. H. Chen, “A Novel Column Block-Based Fault-Tolerant Memory System,” Proc. 2001 VLSI/CAD Workshop, Taoyuan, Taiwan, Aug. 2001.
[92]
S. K. Lu, T. Y. Lee, and C. W. Wu, “A Profit Evaluation (PES) for Logic Cores at Early Design Stage,” Proc. Int. Conf. Electronic Circuits and Systems (ICECS2001), pp. 1491-1494.
[93]
S. K. Lu and Chih-Hsien Hsu, “Built-In Self-Repair for Divided Word Line Memory,” Proc. Int. Symp.Circuits and Systems (ISCAS2001), pp. IV13-IV16.
[94]
S. K. Lu and Jen-Sheng Shih, and Cheng-Wen Wu, “BIST and Diagnosis of Fully Logic Blocks in FPGAs,” Proc. 2000 VLSI/CAD Workshop, pp. 413-416, KengDing, Taiwan, Aug. 2000.
[95]
S. K. Lu and Chih-Hsien, “Built-In Self-Repair for Divided Word Line Memory,” Proc. 2000 VLSI/CAD Workshop, pp. 405-408, KengDing, Taiwan, Aug. 2000.
[96]
S. K. Lu, J. S. Shih, and C. W. Wu, “A Testable/Fault-Tolerant FFT Processor Design,” Proc. Asian Test Symposium, pp. 429-433, Dec. 2000.
[97]
S. K. Lu, J. S. Shih, and C. W. Wu, "Built-In Self-Test and Fault Diagnosis for Lookup Table FPGAs,” Proc. Int. Symp. Circuits and Systems (ISCAS), vol. 1, pp. 80-83, May 2000.
[98]
S. K. Lu and C. W. Wu, "Defect Level Prediction Using Multi-Model Fault Coverage", Proc.Asian Test Symp. (ATS), Shanghai, Nov. 1999.
[99]
S. K. Lu and C. W. Wu, "Defect Level Prediction Using Multi-Model fault Coverage” Proc. 10th Design/CAD Symp., Nantou, pp. 195-198, Aug. 1999.
[100]
S. K. Lu, J. S. Shih, and C. W. Wu, "Testing Configurable LUT-Based FPGA’s,” Proc. 10th Design/CAD Symp., Nantou, pp. 171-174, Aug. 1999.
[101]
S. K. Lu and C. W. Wu, "A Novel Approach to Testing LUT-Based FPGAs", Proc. Int. Symp.Circuits and Systems (ISCAS), vol. 2, pp. 69-72, Orlando, May 1999.
[102]
J. F. Li, S. A. Arn, S. K. Lu and C. W. Wu, "Fault tolerant FFT butterfly network design", Proc VLSI/CAD Workshop, pp. 403-407, Nantou, Taiwan, Aug. 1998.
[103]
S. K. Lu and C. W. Wu, “VLSI design of RSA public-key cryptosystem”, Proc. 1997 ISIC Symposium, pp. 68-71, Singapore, Sep. 1997.
[104]
Y.-N. Rau, W.-Y. Tseng, S.-K. Lu and S.-Y. Kuo, “A 155.52 Mhz SVDCO-based all digital clock recovery circuit for ATM Applications“, Proc. 1996 VLSI/CAD Workshop, pp. 123-126, Shiemen, Taiwan, Aug. 1996.
[105]
S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “On fault-tolerant FFT butterfly network design”, Proc. Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp. 69-72, Atlanta, May 1996.
[106]
S. K. Lu, S. Y. Kuo and C. W. Wu, “Design and Evaluation of Fault-Tolerant Interleaved Memory Systems”, Proc. Asian Test Symp. (ATS), Nara, Nov. 1994, pp. 354-359.
[107]
S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Design of easily testable VLSI arrays for discrete cosine transform“, Proc. IEEE 26th Ann. Asilomar Conf. Signals, Systems, and Computers“, Pacific Grove, Oct. 1992.
[108]
S.-K. Lu, C.-W. Wu and S.-Y. Kuo, “Testable design of systolic arrays for discrete cosine transform, Proc. VLSI/CAD Workshop, pp. 228-237, Nantou, Taiwan, Mar. 1992.
[109]
C.-W. Wu and S.-K. Lu, “Designing self-testable cellular arrays”, Proc. IEEE Int. Conf. Computer Design (ICCD), pp. 110-113, Cambridge, Massachusetts, Oct. 1991.
[110]
C.-W. Wu and S.-K. Lu, “Architecture-Specific Computer-Aided Testing”, Proc. Sino- German CAD/VLSI Workshop, pp. 34-43, Tainan, Taiwan, Sep. 1991.
[111]
C.-W. Wu, S. K. Lu and J.-C. Wang, “Built-in self-test of iterative logic arrays”, Proc. Int. Electron Devices and Material Symposium (EDMS), pp. 485-488, Hsinchu, Taiwan, Nov. 1990.
[1]
“Fault bits scrambling memory and method thereof” 申請日: 2014/3/31，申請號：14/230,554US，美國發明專利。
[2]
“A Fault Masking Method for Non-Volatile Memories” 申請日: 2013/7/17 ，申請號：13/940,353，美國發明專利 (授證中)。
[3]
非揮發性記憶體的資料反轉與回復方法，申請日: 2013/5/13，申請號：102116904，中華民國發明專利。
[4]
非揮發性記憶體的故障遮蔽方法，申請日: 2013/1/16，申請號：102101601，中華民國發明專利。
[5]
具分散錯誤功能的記憶體及其分散錯誤位元的方法，申請日: 2013/7/9，申請號：102124565，中華民國發明專利。
[6]
呂學坤 (2007-2008): 內嵌式記憶體有效之內建資源分析與自我修復技術之研究, 國科會專題研究計畫成果報告
[7]
呂學坤 (2006):前瞻無線測試平台與技術分項計畫 內嵌式記憶體自我測試、故障診斷與修復技術, 國科會專題研究計畫成果報告
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呂學坤 (2006):具易測試性與容錯功能之快速傅立葉轉換器設計技術), 國科會專題研究計畫成果報告
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呂學坤 (2005):內嵌式可程式化邏輯模組功能性測試與診斷技術(2/3), 國科會專題研究計畫成果報告
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呂學坤 (2004): 內嵌式可程式化邏輯模組功能性測試與診斷技術(2/3), 國科會專題研究計畫成果報告
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呂學坤 (2003): 內嵌式可程式化邏輯模組功能性測試與診斷技術(1/3), 國科會專題研究計畫成果報告
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呂學坤 (2002):計算機記憶體系統之容錯架構與診斷技術之研究, 國科會專題研究計畫成果報告
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呂學坤 (2001): 記憶體與邏輯電路診斷技術之研究期末報告，華騰科技
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呂學坤 (2000): 多故障模型損壞位準之分析。國科會專題研究計畫成果報告
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呂學坤 (1999): 使用邊線擴張圖計算網路之端對可靠度。國科會專題研究計畫成果報告
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呂學坤 (1998): 快速傅立葉轉換器之可測試性與容錯設計。國科會專題研究計畫成果報告
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呂學坤、鄭淑蘭；呼吸治療設備，合記圖書，1989
年度
計畫名稱
委託單位
2014
以矽載板為中介層之三維積體電路設計與測試自動化工具研發--子計畫五：使用 TSV 為基礎之三維隨機存取記憶體之測試與修復基礎架構(3/3)
國科會
2013
以矽載板為中介層之三維積體電路設計與測試自動化工具研發--子計畫五：使用 TSV 為基礎之三維隨機存取記憶體之測試與修復基礎架構(2/3)
國科會
2012
以矽載板為中介層之三維積體電路設計與測試自動化工具研發--子計畫五：使用 TSV 為基礎之三維隨機存取記憶體之測試與修復基礎架構(1/3)
國科會
2011
內嵌式記憶體自我修復技術與設計自動化 (3/3)
國科會
2010
無諧波鎖定, 快速鎖定, 全數位式延遲鎖定迴路之研發
國科會
2010
內嵌式記憶體自我修復技術與設計自動化 (2/3)
國科會
2009
內嵌式記憶體自我修復技術與設計自動化 (1/3)
國科會
2008
內嵌式靜態隨機存取記憶體低功率內建自我測試技術之研究
國科會
2007
內嵌式記憶體有效之內建資源分析與自我修復技術之研究 (2/2)
國科會
2006
內嵌式記憶體有效之內建資源分析與自我修復技術之研究 (1/2)
國科會
2005
前瞻無線測試平台與技術分項計畫內嵌式記憶體自我測試、故障診斷與修復技術
國科會
2005
具易測試性與容錯功能之快速傅立葉轉換器設計技術
國科會
2004
內嵌式可程式化邏輯模組功能性測試與診斷技術(3/3)
國科會
2003
內嵌式可程式化邏輯模組功能性測試與診斷技術(2/3)
國科會
2003
提升私校研發能量行動多媒體網路系統技術之研究發展與應用: 子計劃六之一 (III) 無線多媒體單晶片系統之硬體設計
國科會
2002
提升私校研發能量 行動多媒體網路系統技術之研究發展與應用: 子計劃六之一 (II) 無線多媒體單晶片系統之硬體設計
國科會
2002
內嵌式可程式化邏輯模組功能性測試與診斷技術(1/3)
國科會
2001
計算機記憶體系統之容錯架構與診斷技術之研究
國科會
2000
多故障模型損壞位準之分析
國科會
1999
使用OBDD之邊線擴張圖計算網路之端–對可靠度
國科會
1998
快速傅立葉轉換器之可測試性與容錯設計
國科會
年度
計畫名稱
委託單位
2011
教育部智慧電子整合性人才培育先導型計畫智慧電子應用設計聯盟中心計畫
教育部
2010
教育部智慧電子整合性人才培育先導型計畫智慧電子應用設計概論課程開發計畫
教育部
2010
超大形積體電路測試核心課程精進計畫-特殊半導體記憶體測試
教育部
2010
前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心 99 年度計畫
教育部
2009
前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心 98 年度計畫
教育部
2009
教育部前瞻晶片系統設計 (SOC) 學程計畫: 嵌入式系統軟體學程
教育部
2008
電子資訊科技於醫療照護之研究與應用 (2/3)
輔仁大學
2008
內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (4/4)
經濟部
2008
前瞻晶片系統設計人才培育先導型計畫—設計自動化與測試 (DAT) 聯盟中心97年度計畫
教育部
2007
內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (3/4)
經濟部
2007
記憶體測試非同步教材開發
教育部
2007
電子資訊科技於醫療照護之研究與應用 (1/3)
輔仁大學
2007
前瞻晶片系統設計 (SOC) 學程計畫
教育部
2006
內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (2/4)
經濟部
2005
教育部「超大型積體電路與系統設計教育改進計畫」課程推廣
教育部
2005
內嵌式記憶體自我測試、診斷與修復之無線測試平台與技術開發與研究 (1/4)
經濟部
2005
VLSI與系統設計教育改進計畫-EDA聯盟進階測試課程
教育部
2004
創造力在積體電路與系統領域之發模式教材發展計畫(第三年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計
教育部
2004
VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術
教育部
2004
VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫
教育部
2003
大學科技系所人才培育計畫-「積體電路設計課程教學改善計畫」
教育部
2003
創造力在積體電路與系統領域之發模式教材發展計畫(第二年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計
教育部
2003
VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術
教育部
2003
VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫
教育部
2002
創造力在積體電路與系統領域之發模式教材發展計畫(第一年) –單晶片系統內嵌式記憶體測試、診斷與修復之創意設計
教育部
2002
VLSI與系統設計教育改進計畫-EDA聯盟測試課程:單晶片系統核心診斷技術
教育部
2002
VLSI與系統設計教育改進計畫-EDA聯盟VTTF 計畫
教育部
2002
VLSI 改進計劃邏輯診斷技術分項計劃
教育部
2001
單晶片系統邏輯核心效益評估系統
教育部
2000
使用邏輯模擬器作 Stuck-at故障之定位
教育部
2000
教育部第二期 VLSI 改進計劃
教育部
2000
記憶體與邏輯電路診斷技術之研究
Syntest 華騰科技
1998
教育部第一期VLSI 改進計劃
教育部