| ENGLISH |
|
|
| |
| 【期刊論文】 |
|
| [1] |
Chia-Yu Yao and Wei-Chun Hsia, “An Indoor Positioning System Based on the Dual-Channel Passive RFID Technology,” IEEE Sensors Journal, vol. 18, no. 11, June 1, 2018. (SCI, EI) (MOST 105-2221-E-011-145-MY2) |
|
| [2] |
Chia-Yu Yao, Shui-Chin Wang, and Cheng-Hung Yu,“Fee collection plan for plug-in electric vehicles charged in nonresidential parking lots with minimum hardware investment: a study of Asian megacities,” Journal of the Chinese Institute of Engineers, vol. 41, no. 3, pp. 186-193, May 2018. (SCI, EI) (MOST 105-2221-E-011-145-MY2) |
|
| [3] |
Yung-Hsiang Ho and Chia-Yu Yao, “A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation," IEEE Trans. VLSI Syst., vol. 24, no. 5, pp. 1984-1992, May 2016. (SCI, EI) (MOST 103-2221-E-011-059) |
|
| [4] |
Chia-Yu Yao and Wei-Chun Hsia, “A Dual-Band UHF Passive CMOS RFID Tag with an Easily Matched Charge Pump,” Int. J. of Electrical Engineering, vol. 23, no. 2, pp. 45-51, Apr. 2016. (EI) (MOST 103-2221-E-011-059) |
|
| [5] |
Yung-Hsiang Ho and Chia-Yu Yao, “A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register,” IEEE Trans. VLSI Syst., vol. 24, no. 2, pp. 759-763, Feb. 2016. (SCI, EI) (MOST 103-2221-E-011-059) |
|
| [6] |
Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, and Rong-Jyi Yang, “A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter with Cycle-Controlled DPWM,” IEEE Trans. VLSI Syst., vol. 24, no. 1, pp. 17-25, Jan. 2016. (SCI, EI). |
|
| [7] |
Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, and Rong-Jyi Yang, “Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line,” IEEE Trans. VLSI Syst., vol. 23, no. 3, pp. 567-574, Mar. 2015. (SCI, EI) (NSC 101-2221-E-011-168) |
|
| [8] |
Chia-Yu Yao, Wei-Chun Hsia, and Yu-Jou Wen, “The Soft- Injection-Locked Ring Oscillator and its Application in a Vernier-Based TDC,” IEEE Trans. Instrum. Meas., vol. 63, no. 8, pp. 2064-2071, Aug. 2014. (SCI, EI) (NSC 101-2221-E-011-168) |
|
| [9] |
Chia-Yu Yao and Wei-Chun Hsia, “A –21.2-dBm Dual-Channel UHF Passive CMOS RFID Tag Design,” IEEE Trans. Circuits Syst. I, vol. 61, no. 4, pp. 1269-1279, Apr. 2014. (SCI, EI) (NSC 100-2221-E-011-095) |
|
| [10] |
Chia-Yu Yao, Wei-Chun Hsia, and Yung-Hsiang Ho, “Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space,” IEEE Trans. Circuits Syst. I, vol. 61, no. 1, pp. 202-212, Jan. 2014. (SCI, EI) (NSC 98-2221-E-011-085) |
|
| [11] |
姚嘉瑜, 夏偉鈞, 蔡佩容, 溫鈺柔, “使用軟注入鎖定環形振盪器之游標卡尺法時間至數位轉換器,” 科儀新知, 34卷, 第2期, pp. 19-27, 2012年10月。 |
|
| [12] |
Chia-Yu Yao, “The Design of Hybrid Asymmetric-FIR/Analog Pulse-Shaping Filters Against Receiver Timing Jitter,” IEEE Trans. Commun., vol. 60, no. 5, pp. 1199-1203, May 2012. (SCI, EI) (NSC 99-2221-E-011-144) |
|
| [13] |
Chia-Yu Yao and Alan N. Willson, Jr., “The Design of Hybrid Symmetric-FIR/Analog Pulse-Shaping Filters,” IEEE Trans. Signal Processing, vol. 60, no. 4, pp. , April 2012. (SCI, EI) (NSC 99-2221-E-011-144) |
|
| [14] |
Chia-Yu Yao, “A design method of hybrid analog/asymmetrical-FIR pulse-shaping filters,” ETRI Journal, vol. 32, no. 6, pp. 911-920, Dec. 2010. (SCI, EI) (NSC 98-2221-E-011-085) |
|
| [15] |
Chia-Yu Yao and Chih-Chun Hsieh, “Hardware simplification to the delta path in a MASH 111 delta-sigma modulator,” IEEE Trans. Circuits Syst. II, vol. 56, no. 4, pp. 270-274, April 2009. (NSC 97-2221-E-011-139) (SCI, EI) |
|
| [16] |
Chia-Yu Yao and Chin-Chih Yeh, “An application of the second-order passive lead-lag loop filter for analog PLLs to the third-order charge-pump PLLs,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 972-974, Feb. 2008. (SCI, EI) (NSC 95-2221-E-011-214) |
|
| [17] |
Chia-Yu Yao, Hsin-Horng Chen, Chiang-Ju Chien, and Chun-Te Hsu, “A high-level synthesis procedure for linear-phase fixed-point FIR filters with SPT coefficients,” Int. J. of Electrical Engineering, vol. 12, no. 1, pp. 75-84, Feb. 2005. (SCIE, EI) (NSC 92-2218-E-211-002) |
|
| [18] |
Chia-Yu Yao, Jen-Wei Tsai, and Jou-Hung Wang, “A novel VCO structure with five interlocked ring oscillators,” J. of the Chinese Institute of Electrical Engineering, vol. 9, no. 4, pp. 401-406, Nov. 2002. (EI) |
|
| [19] |
Chiang-Ju Chien and Chia-Yu Yao, “An output based adaptive iterative learning controller for high relative degree uncertain linear systems,” Automatica, vol. 40, no. 1, pp. 145-153, 2004. (SCI, EI) (NSC 90-2213-E-211-002) |
|
| [20] |
Chiang-Ju Chien and Chia-Yu Yao, “Iterative learning of model reference adaptive controller for uncertain nonlinear systems with only output measurement,” Automatica, vol. 40, no. 4, pp. 855-864, 2004. (SCI, EI) (NSC 90-2213-E-211-002) |
|
| [21] |
Chiang-Ju Chien, Chun-Te Hsu, and Chia-Yu Yao, “Fuzzy system based adaptive iterative learning control for nonlinear plants with initial state errors,” IEEE Transactions on Fuzzy Systems, vol. 12, no. 5, pp. 724-732, 2004. (SCI, EI) |
|
| [22] |
Chia-Yu Yao, Hsin-Horng Chen, Tsuan-Fan Lin, Chiang-Ju Chien, and Chun-Te Hsu, “A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters,” IEEE Trans. Circuits Syst. I., vol. 51, no. 11, pp. 2215-2221, Nov. 2004. (SCI, EI) (NSC 92-2218-E-211-002) |
|
| [23] |
Chia-Yu Yao, “The design of square-root-raised-cosine FIR filters by an iterative technique,” IEICE Trans. on Fundamentals, vol. E90-A, no. 1, pp. 241-248, Jan. 2007. (SCI, EI)(NSC 94-2215-E-011-007) |
|
| [24] |
Chia-Yu Yao, Chun-Te Hsu, and Chiang-Ju Chien, “Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized Discrete-Time Models,” IEICE Trans. Electronics., vol. E90-C, no. 3, pp.628-633, March 2007. (SCI, EI) (NSC94-2215-E-011-007) |
|
| [25] |
Chia-Yu Yao and Chiang-Ju Chien, “A partial MILP algorithm for the design of linear phase FIR filters with SPT coefficients,” IEICE Trans. Fundamentals, vol. E85-A, no. 10, pp. 2302-2310, Oct. 2002. (SCI, EI) |
|
| [26] |
Chia-Yu Yao and Jen-Wei Tsai, “Programmable divide-by-N counter with 50% duty cycle output,” Electronics Letters, vol. 35, no. 8, pp. 624-625, April 1999. (SCI, EI) |
|
| |
|
| |
| 【研討會論文】 |
|
| [1] |
Chia-Yu Yao, Wei-Chun Hsia, and Chien-Te Yu, “Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo,” in Proc. 2018 IEEE Int. Symp. Circuits and Systems, Florence, Italy, May 2018, pp. 1-4. |
|
| [2] |
Chia-Yu Yao, “Jitter Insensitivity SR Filter Design for Digital Baseband Transceiver ICs,” 4th International Forum on Advanced Technologies, Tokushima, Japan, March 2018. |
|
| [3] |
Chia-Yu Yao and Shui-Chin Wang, “A QCQP Design method of the Symmetric Pulse-Shaping Filters Against Receiver Timing Jitter”, in Proc. 2017 IEEE Int. Symp. Circuits and Systems, Baltimore, USA, May 2017, pp. 1954-1957. |
|
| [4] |
Chia-Yu Yao, “A Simulation Technique of Delta-Sigma Modulator Circuits,” 3rd International Forum on Advanced Technologies, Taroko, Hualian, Taiwan, March 2017. |
|
| [5] |
Chia-Yu Yao, “Experimenting with error performance of systems employing pulse shaping filters on a software-defined-radio platform,” in Proc. 2016 WASET 18th International Conference on Communications, Control and Information Technology, Zurich, Switzerland, July 2016. (MOST 104-2221-E-011-121) |
|
| [6] |
Chia-Yu Yao, “A Phase-Frequency Error Compensator for an All-Digital Fast-Locked PLL Frequency Synthesizer,” 2nd International Forum on Advanced Technologies, Tokushima, Japan, March 2016. |
|
| [7] |
Yung-Hsiang Ho and Chia-Yu Yao, “A novel starting-bit prediction algorithm for the SAR-based delay-locked loop,” in Proc. 2015 VLSI Design/CAD Symp., Hualien, Aug. 2015. (MOST 103-2221-E-011-059) |
|
| [8] |
Chia-Yu Yao and Wei-Chun Hsia, “A Dual-band UHF Passive CMOS RFID Tag with an easily matched charge pump,” in Proc. 2015 VLSI Design/CAD Symp., Hualien, Aug. 2015. (MOST 103-2221-E-011-059) |
|
| [9] |
Chia-Yu Yao, Yung-Hsiang Ho, and Wei-Chun Hsia, and Jyun-Jie Huang, “Simulating Delta-Sigma Analog-to-Digital Converters with the Op-Amp Nonlinearity using the Newton’s Method,” in Proc. 2015 IEEE Int. Symp. Circuits and Systems, Lisbon, Portugal, May 2015, pp. 537-540. (MOST 103-2221-E-011-059) |
|
| [10] |
Chia-Yu Yao, Yi-Yao Chiu, and Yung-Hsiang Ho, “A 33 Lock-Cycle SAR-based ADDLL Using a Resettable Delay Line,” in Proc. 2013 VLSI Design/CAD Symp., Kaohsiung, Aug. 2013. |
|
| [11] |
M.-H. Lee, C.-Y. Yao, and H.-C. Liu, “Passive tag for multi-carrier RFID systems,” Proc. Int. Conf. Parallel and Distributed Systems - ICPADS, Tainan, Dec. 2011, pp. 872-876. |
|
| [12] |
Yung-Hsiang Ho and Chia-Yu Yao, “Using 2-Bit Counter to Predict the Starting SAR-Bit for a Fast-Locking Wide-Range All-Digital DLL,” in 2013 IEEE-UFFC Joint Symposia, Prague, July 2013. |
|
| [13] |
Yung-Hsiang Ho and Chia-Yu Yao, “A low-phase-noise 4.72-5.58-GHz LC-VCO design,” in 2013 IEEE-UFFC Joint Symposia, Prague, July 2013. |
|
| [14] |
Ming-Hsien Lee, Chia-Yu Yao, Muhammad Khaerul Naim, and Hsin-Chin Liu, “Demodulator for multi-carrier UHF RFID tags,” in Proc. The 17th IEEE Int. Symp. Consumer Electronics, Hsinchu, Taiwan, June 2013, pp. 5-6. |
|
| [15] |
Yi-Chia Lee, Chia-Yu Yao, Cheng-Yu Hsieh, Jau-Yi Wu, Yi-Hsuan Hsieh, Chien-Hsiung Chen, Rung-Huei Liang, and Ya-Shu Chen, “Egg Pair-A Hearing Game for the Visually Impaired People Using RFID,” in Proc. The 17th IEEE Int. Symp. Consumer Electronics, Hsinchu, Taiwan, June 2013, pp. 3-4. |
|
| [16] |
Chia-Yu Yao and Yung-Hsiang Ho, “A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism,” in Proc. 2013 Int. Symp. VLSI Design, Automation, and Test, Hsinchu, Taiwan, April 2013, pp. 287-290. |
|
| [17] |
Chia-Yu Yao, Wei-Chun Hsia, and Yi-Hsin Ko, “A dual-channel UHF passive CMOS RFID tag design,” in Proc. 2012 Asia-Pacific Microwave Conf., Kaohsiung, Taiwan, Dec. 2012, pp. 1145-1147. |
|
| [18] |
Chia-Yu Yao, Yung-Hsiang Ho and Wei-Chun Hsia, “Optimization of the hybrid asymmetric- FIR/analog square-root filters,” in Proc. 2012 IEEE Int. Symp. Intelligent Signal Processing and Commun. Syst., Nov. 2012, pp. 395-400. |
|
| [19] |
Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, and Chao-Chyun Chen, “A wide-Range all-digital delay-locked loop using fast-lock variable SAR algorithm,” in Proc. 2012 IEEE Int. Symp. Intelligent Signal Processing and Commun. Syst., Nov. 2012, pp. 338-342. |
|
| [20] |
Chia-Yu Yao, Wei-Chun Hsia, and Yi-Hsin Ko, “Ultra low-power dual-band UHF passive CMOS RFID tag design,” in Proc. 4th Int. Symp. Microchemistry and Microsystems, Hsinchu, Taiwan, June 2012, pp. 378-379. |
|
| [21] |
Chia-Yu Yao, Wei-Chun Hsia, Pei-Jung Tsai, and Yu-Jou Wen, “The vernier-based TDC employing soft-injection-locked ring oscillators,” in Proc. 2012 IEEE Int. Instrum. and Meas. Tech. Conf., May 2012, pp. 2291-2294. |
|
| [22] |
Pei-Jung Tsai and Chia-Yu Yao, “Soft-injection-locked ring oscillator and its application in time period measurement,” 2012年智慧電子應用設計研討會，桃園，Feb. 2012, pp. 8-12. |
|
| [23] |
Chia-Yu Yao, Wei-Chun Hsia, and Yi-Hsin Ko, “A highly efficient UHF passive CMOS RFID tag,” in Proc. 2011 VLSI Design/CAD Symp., Yun-Lin, Aug. 2011, pp. 200-203. (NSC 99-2221-E-011-144) |
|
| [24] |
Chia-Yu Yao, “The jitter insensitive pulse-shaping filter design,” in Proc. 2011 WASET Int. Conf. Elect., Comput., Electron., Commun., Amsterdam, Netherland, July 2011, pp. 380-383. (NSC 99-2221-E-011-144) |
|
| [25] |
Chia-Yu Yao and Chung-Lin Sha, “Fixed-point FIR filter design and implementation in the expanding subexpression space,” in Proc. 2010 IEEE Int. Symp. Circuits and Systems, Paris, France, May 2010, pp. 185-188. (NSC 97-2221-E-011-139). |
|
| [26] |
Chia-Yu Yao and Chung-Lin Sha, “Fixed-point FIR Filter Design and Implementation in the Expanded Subexpression Space,” in Proc. 2009 VLSI Design/CAD Symp., Hua-Lien, Aug. 2009. |
|
| [27] |
Chia-Yu Yao and Chih-Chun Hsieh, “Hardware simplification to the delta path in a MASH 111 delta-sigma modulator,” in Proc. National Symposium on Telecommunications, 2008, Yunlin, Dec. 2008. |
|
| [28] |
Chia-Yu Yao and Alan N. Willson, Jr., “The Design of Asymmetrical Square-Root Pulse-Shaping Filters with Wide Eye-Openings”, in Proc. 2008 IEEE Int. Symp. Circuits and Systems, Seattle, USA, May 2008, pp. 2665-2668. |
|
| [29] |
Chia-Yu Yao, “A Design Method of FIR Filters for QAM Applications,” in Proc. National Symposium on Telecommunications, 2007, Taipei, Nov. 2007, pp. 1099-1103. |
|
| [30] |
Chia-Yu Yao, Chun-Te Hsu, and Chih-Chun Hsieh, “Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized Discrete-Time Models,” in Proc. IEEE TENCON 2007, Taipei, Oct. 2007. (NSC 94-2215-E-011-007) |
|
| [31] |
Chia-Yu Yao, Chun-Te Hsu, and Chih-Chun Hsieh, “Stability Analysis of Fourth-Order Charge-Pump PLLs using Linearized Discrete-Time Models,” in Proc. 2007 VLSI Design/CAD Symp., Hua-Lien, Aug. 2007, pp. 5-8. |
|
| [32] |
Chia-Yu Yao and Alan N. Willson, Jr., “The design of symmetric square-root pulse-shaping filters for transmitters and receivers,” in Proc. 2007 IEEE Int. Symp. Circuits and Systems, New Orleans, USA, May 2007, pp.2056-2059. (EI) (NSC 95-2221-E-011-214) |
|
| [33] |
Chia-Yu Yao, Chun-Te Hsu, and Chin-Chih Yeh, “The analysis of phase-jitter variance in the third-order CPPLL frequency synthesizer,” in Proc. IEEE 2006 Asia-Pacific Conf. Circuits Systems, Singapore, Dec. 2006, pp. 1045-1048. (EI) (NSC 94-2215-E-011-007) |
|
| [34] |
姚嘉瑜、王明傑、褚芳達, “高精確度低成本計時卡之研發,” 2006時頻技術與業務推廣研討會, 中華電信研究所, 2006年8月31日, pp. 46-51. |
|
| [35] |
Chia-Yu Yao, Chun-Te Hsu, and Chin-Chih Yeh, “The Derivation of Phase-Jitter Variance for the Third-Order Charge-Pump PLL Frequency Synthesizer,” in Proc. 2006 VLSI Design/CAD Symp., Hua-Lien, Aug. 2006, pp. 209-212. |
|
| [36] |
Chia-Yu Yao, Chin-Chih Yeh, and Chun-Te Hsu, “The analysis of phase-jitter variance for the second-order CPPLL frequency synthesizer,” in Proc. ICCCAS2006, GuiLin, China., June 2006, pp. 2503-2506. (NSC 94-2215-E-011-007) |
|
| [37] |
Chia-Yu Yao and Chiang-Ju Chien, “The design of a square-root-raised-cosine FIR filter by a recursive method,” in Proc. 2005 IEEE Int. Symp. Circuits and Systems, Kobe, Japan, May 2005, pp.512-515. (NSC 93-2215-E-211-004) |
|
| [38] |
Chia-Yu Yao, Hsin-Horng Chen, Tsuan-Fan Lin, Chiang-Ju Chien, and Chun-Te Hsu, “A new common-subexpression-sharing method for the synthesis of FIR filters,” in Proc. IEEE 2004 Asia- Pacific Conf. Circuits Systems, Tainan, Taiwan, R.O.C., Dec. 2004, pp. 701-704. (NSC 92-2218-E-211-002) |
|
| [39] |
Chun-Te Hsu, Chiang-Ju Chien, Hsin-Hui Chiang, and Chia-Yu Yao, “FPGA implementation of a fuzzy logic controller using VHDL,” 2004 National Conference on Fuzzy Theory and Its Applications, Taiwan, R.O.C., Nov., 2004. |
|
| [40] |
Chun-Te Hsu, Chiang-Ju Chien, Hsin-Hui Chiang, Chia-Yu Yao, and Tz-Ming Wu, “The FPGA Realization of an Iterative Learning Control Algorithm,” 2004 R.O.C. Automatic Control Conference, Taiwan, R.O.C., Mar. 2004. |
|
| [41] |
Chun-Te Hsu, Chiang-Ju Chien, and Chia-Yu Yao, and Yen-Ko Chiang, “The design and application of a self-organized fuzzy system,” 2003 The Joint Conference on AI, Fuzzy System and Grey System, Taipei, Taiwan, R.O.C., December, 2003. |
|
| [42] |
Chia-Yu Yao and Calvin Chen, “Development of 2.4 GHz Stereo Digital Wireless Speakers and Headphones,” Proc. 2003 Workshop on Consumer Electronics, Tainan, Nov. 2003. (NSC91-2622- E-211-004-CC3). |
|
| [43] |
Chun-Te Hsu, Chiang-Ju Chien, and Chia-Yu Yao, “A New Algorithm of Adaptive Iterative Learning Control for Uncertain Robotic Systems,” Proc. 2003 IEEE International Conference on Robotics and Automation, pp. 4130-4135, Taipei, Taiwan, Sep. 2003. (EI) (NSC 90-2213-E-211- 002) |
|
| [44] |
Chia-Yu Yao, Hsin-Horng Chen, and Chiang-Ju Chien, “A high-level synthesis procedure for fixed-point high-speed FIR filters with signed-powers-of-two Coefficients,” Proc. 14th VLSI Design CAD Symposium, Hua-Lein, Aug. 2003, pp.313-316. |
|
| [45] |
Chia-Yu Yao, Chin-Chih Yeh, Tsuan-Fan Lin, Hsin-Horng Chen, and Chiang-Ju Chien, “A design flow for linear-phase fixed-point FIR filters: from the NPRM specifications to a VHDL code,” in Proc. 2003 IEEE Int. Symp. Circuits and Systems, vol. IV, Bangkok, Thailand, May 2003, pp.277-280. (EI)(NSC90-2215-E-211-001) |
|
| [46] |
Chun-Te Hsu, Chiang-Ju Chien, and Chia-Yu Yao, “A New Algorithm of Adaptive Iterative Learning Control for Uncertain Robotic Systems,” 2003 R.O.C. Automatic Control Conference, pp. 829-834, Taiwan, R.O.C., Mar. 2003. |
|
| [47] |
Chiang-Ju Chien, Chun-Te Hsu and Ch-a-Yu Yao, “Fuzzy system based adaptive iterative learning controller for nonlinear plants with initial state errors,” 2002 R.O.C. Automatic Control Conference, pp. 316–321, Taiwan, R.O.C., Mar. 2002. |
|
| [48] |
Tsuan-Fan Lin, Hsin-Horng Chen, and Chia-Yu Yao, “Design and analysis of the VHDL program generator for linear-phase FIR filters,” Proc. 2002 Nat’l Symp. on Telecommunications, PDSP1-4, Nan-Toe, Taiwan, Dec. 2002. |
|
| [49] |
Chia-Yu Yao, Jou-Hung Wang, and Chiang-Ju Chien, “A design recipe of charge-pump PLL frequency synthesizer,” Proc. IEEE Int’l Symp. on Intelligent Signal Processing and Communication Systems, Kaohsiung, Taiwan, ROC, Nov. 2002, pp. 478–482. (EI) |
|
| [50] |
Chia-Yu Yao, Jen-Wei Tsai, and Jou-Hung Wang, “A Novel Design of VCO with Interlocking Ring Oscillators,” Proc. Int’l Symp. on Communications, Tainan, Nov. 2001. |
|
| [51] |
Chia-Yu Yao, Jen-Wei Tsai, Chin-Chih Yeh, and Jou-Hung Wang, “A comparison of phase-noise in three ring-oscillator structures,” Proc. 12th VLSI Design CAD Symposium, Hsin-Chu, Aug. 2001. |
|
| [52] |
Chia-Yu Yao, “A study of SPT-term distribution of CSD numbers and its application for designing fixed-point linear phase FIR filters,” Proc. 2001 IEEE Int’l Symp. on Circuits and Systems, vol. II, Sydney, Australia, May 2001, pp.301-304. (EI) |
|
| [53] |
Chin-Chih Yeh and Chia-Yu Yao, “A heuristic algorithm for the design of linear phase FIR filters with signed-powers-of-two coefficients,” Proc. 2000 Nat’l Symp. on Telecommunications, vol. 1, Chung-Li, Taiwan, Dec. 2000, pp. 223-228. |
|
| [54] |
Chia-Yu Yao, “A CMOS 2.5V 1GHz frequency synthesizer design,” 1999 Fall Workshop on Information Theory & Communications, Sep. 1999. |
|
| [55] |
Chia-Yu Yao, et al., “Some measured bit error rate and burst errors of the fixed indoor wireless channels,” Proc. TANET’98, Hualein, Nov. 1998. |
|
| [56] |
Chia-Yu Yao, et al., “64Kbps wireless modem prototype design and channel measurement,” HP EESof User’s Group Meeting, Taipei, Aug. 1998. |
|
| [57] |
Daniel Lee, Chuan-Yi Tang, Jywe-Fei Fang, Chia-Yu Yao, and In-Jen Lin, “Parallel iterative methods – pipelined iterative methods on combustion problem,” Proc. 10th Int’l Conf. on Parallel CFD, May 1998. |
|
| [58] |
Chia-Yu Yao, “An adaptive antenna beamformer for wireless LAN,” 1998 IEEE Spring Workshop on Information Theory & Communications, Taipei, Feb. 1998. |
|
| [59] |
Chia-Yu Yao, et al., “A new DDFS design employing perceptron,” Proc. 7th VLSI Design CAD Symposium, Tao-Yuan, 1996. |
|
| [60] |
Chia-Yu Yao, “How to implement negative resistors in an electric analog neural network,” Proc. Int’l Conf. on Neural Information Processing, Seoul, 1994. |
|
| [61] |
Chia-Yu Yao, “A remote active phase estimation method for active noise control,” Proc. Int’l Symp. on Communications, pp.1325-1332, Hsin-Chu, 1993. |
|
| [62] |
Wei-Chung Peng, Chia-Yu Yao, Henley Woo, A. Caroglanian, and L. Piotrowski, “A multipath propagations study using CLASS,” Proc. MILCOM’92, 1992. |
|
| [63] |
Chia-Yu Yao and A. N. Willson, Jr., “One-neuron circuitry for carry generation in a 4-bit adder,” Proc. Int’l Joint Conf. on Neural Networks, Baltimore, June 1992. |
|
| [64] |
Chia-Yu Yao, Wei-Chung Peng, Dennis Lai, and Roger Avant, “An analysis on the STGT MA phase calibration,” Proc. Int’l Symp. on Communications, Tainan, Dec. 1991. |
|
| [65] |
Chia-Yu Yao and A. N. Willson, Jr., “A neural network approach to statistical decision making,” Proc. IEEE Int’l Symp. on Circuits and Systems, New Orleans, May 1990. (EI) |
|
| [66] |
Soochang Pei and Chia-Yu. Yao, “A personal-computer based speaker dependent speech recognition system,” Proc. of the National Control Conf., Taiwan, Nov. 1985. |
|
| |
|
| |
| 【專利、專書、技術報告】 |
|
| [1] |
Chia-Yu Yao, “Optimizing symmetrical square-root FIR filter design against receiver clock jitter,” 科技部成果報告, MOST 103-2221-E-011-059. |
|
| [2] |
Chia-Yu Yao, “The Design of the Next Generation Passive RFID Chips and Their Application in the Positioning System (II),” 國科會成果報告, NSC 101-2221-E-011-168. |
|
| [3] |
Chia-Yu Yao, “The Design of the Next Generation Passive RFID Chips and Their Application in the Positioning System (I),” 國科會成果報告, NSC 100-2221-E-011-095. |
|
| [4] |
Chia-Yu Yao, “The Compensation of Signal Distortion by Analog Frontend,” 國科會成果報告, NSC 99-2221-011-144. |
|
| [5] |
Chia-Yu Yao, “The Design of Hybrid Symmetrical-FIR/Analog Pulse-Shaping Filters,” 國科會成果報告, NSC 98-2221-E-011-085. |
|
| [6] |
Chia-Yu Yao, “Synthesis of Integer-Coefficient digital Filters - Design Automation from System Specifications to Realization (II),” 國科會成果報告, NSC 97-2221-E-011-139. |
|
| [7] |
Chia-Yu Yao, “Synthesis of Integer-Coefficient digital Filters - Design Automation from System Specifications to Realization (I),” 國科會成果報告, NSC 96-2221-E-011-175. |
|
| [8] |
Chia-Yu Yao, “A Design Method of FIR Filters for QAM Applications” 國科會成果報告, NSC 95-2221-E-011-214. |
|
| [9] |
Chia-Yu Yao, “A fast design method of fixed-point coefficients for constant multiplications by dynamic programming,” 國科會成果報告, NSC 94-2215-E-011-007 |
|
| [10] |
Wei-Chung Peng, Chia-Yu Yao, Henley Woo, and A. Caroglanian, “A Multipath Propagation Study Using CLASS,” Technical report of LinCom Corporation, 1991. |
|
| [11] |
Chia-Yu Yao, The Generalized Hopfield Network and its Application. Ph.D. dissertation of UCLA, 1992. |
|
| [12] |
Chia-Yu Yao, “A New DDFS Design Employing Perceptron,” 國科會成果報告, NSC83-0404-E-211-001, 1995. |
|
| [13] |
Chia-Yu Yao, “A New Active Noise Control Using Remote Sinusoidal Reduction Method,” 國科會成果報告, NSC84-2213-E-211-003, 1995. |
|
| [14] |
Chia-Yu Yao, “An Adaptive Antenna Beamformer for Wireless LAN: Algorithm and Realization”, 國科會成果報告, NSC86-2213-E-211-006, 1996. |
|
| [15] |
姚嘉瑜, “VLSI 電路設計導論,” 87年度大學校院VLSI科技教育改進計畫, 1998. |
|
| [16] |
Chia-Yu Yao, “A VHDL Program Generator for Linear Phase FIR Filters with Signed-Powers-of- Two Coefficients,” 國科會成果報告, NSC90-2215-E-211-001, 2002. |
|
| [17] |
Chia-Yu Yao, “Development of 2.4 GHz Stereo Digital Wireless Speakers and Headphones,” 國科會成果報告, NSC91-2622- E-211-004-CC3, 2003. |
|
| [18] |
Chia-Yu Yao, “A VHDL Program Generator for FIR Filters with Signed-Powers-of-Two Coefficients in Communication Baseband Signal Processing,” 國科會成果報告, NSC 92-2218- E-211-002, 2004. |
|
| [19] |
Chia-Yu Yao, “A high-level synthesis procedure for symmetric, antisymmetric, and asymmetric fix-point FIR filter coefficients,” 國科會成果報告, NSC 93-2215-E-211-004. |
|
|
| |
|
| |